Keynote speakers - IEEE ICECS2024

Eleni Diamanti is CNRS research director at the LIP6 laboratory of Sorbonne University in Paris. She received her Diploma in Electrical and Computer Engineering from the National Technical University of Athens in 2000 and her PhD in Electrical Engineering from Stanford University in 2006. She then worked as a Marie Curie postdoctoral researcher at the Institute of Optics Graduate School in Palaiseau before joining the CNRS in 2009. Her research focuses on experimental quantum cryptography and communication, and on the development of photonic resources and applications for quantum networks. She is a recipient of a European Research Council Starting Grant, coordinator of the Paris Centre for Quantum Technologies, and was awarded the CNRS silver medal in 2024. She is also cofounder and scientific advisor of the start-up company Welinq that specializes in quantum interconnect technology.

Title: Secure communications in quantum networks

Abstract:

Quantum technologies have the potential to improve in an unprecedented way the security and efficiency of communications in network infrastructures. We discuss the current landscape in quantum communication and cryptography, and focus in particular on high-performance implementations of quantum key distribution, offering security guarantees impossible to achieve with only classical resources. We also describe current challenges in this field and our efforts towards the miniaturization of the developed photonic systems, their deployment into telecommunication network infrastructures, including with satellite links, highlighting the importance of the use of advanced signal processing and electronics technology. These advances enrich the resources and applications of the emerging quantum networks that will play a central role in the context of future global-scale quantum-safe communications.

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a Visiting Professor at Stanford University and a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received various honors for his research, including the Persistent Impact Prize of the Non-Volatile Memory Systems Workshop, the Intel Outstanding Researcher Award, the IEEE High Performance Computer Architecture Test of Time Award, the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award and a healthy number of best paper or “Top Pick” paper recognitions at various computer systems, architecture, and security venues. He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage.

Title: Memory-Centric Computing

Abstract:

Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency, and scalability are bottlenecked by data movement. In this talk, we describe three major shortcomings of modern architectures in terms of 1) dealing with data, 2) taking advantage of the vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent architecture should be designed to handle data well. We posit that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give several examples for how to exploit each of these principles to design a much more efficient and high performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising directions: 1) processing using memory, which exploits analog operational properties of memory chips to perform massively-parallel operations in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory controllers, the logic layer of 3D-stacked memory technologies, or memory chips to enable high memory bandwidth and low memory latency to near-memory logic. We show both types of architectures can enable orders of magnitude improvements in performance and energy consumption of many important workloads, such as graph analytics, database systems, machine learning, video processing, climate modeling, genome analysis. We discuss how to enable adoption of such fundamentally more intelligent architectures, which we believe are key to efficiency, performance, and sustainability. We conclude with some research opportunities in and guiding principles for future computing architecture and system designs.

Some related resources are mentioned below.

A 2-page overview paper from DAC 2023: “Memory-Centric Computing”

A short vision paper from DATE 2021: “Intelligent Architectures for Intelligent Computing Systems”

A longer survey of modern memory-centric computing ideas & systems (updated August 2022): “A Modern Primer on Processing in Memory”

Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. He is the CASS representative at the IEEE IoT Technical Committee. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award and the 2024 Best Associate Editor of IEEE CASS Magazine. He is also Distinguished Lecturer of IEEE CEDA (2024-2025). For more information, please see this webpage.

Title: SoC Power Optimization

Abstract:

The always increasing transistor count in modern systems on chip (SoC), as well the exploding number of devices connected to the internet of things, is demanding new design approaches. One fundamental issue and challenge is the design optimization, mainly power optimization. In some applications, as implantable devices, reliability and power optimization are fundamental. It will be presented an overview of some techniques for power optimization at different levels of design abstraction. The physical design optimization is becoming a more and more important issue, not only for power optimization, but also for connections and vias optimization, increasing routability as well reliability. A large set of circuits are using much more transistors than needed. It will be shown some techniques and examples of design optimization at architectural and physical design level.